The present invention generally relates to a semiconductor device including a DRAM (Dynamic Random Access Memory) memory cell and a manufacturing method of the same. More particularly, the present invention relates to a semiconductor device incorporating a logic transistor therein, and a manufacturing method of the same.
Recent progress in semiconductor fine processing technology has enabled semiconductor elements integrated at 1-giga level to be formed on a single semiconductor LSI (Large-Scale Integration). Thus, a system that is conventionally formed from several semiconductor LSIs of separate chips is about to be formed on a single chip (system on silicon). The current main technology for implementing this system is an embedded DRAM (e-DRAM), i.e., integration of a high-speed logic LSI with a DRAM, a mass-storage general-purpose memory.
A memory cell in the DRAM is formed from a capacitor having a capacity insulating film, and a MIS (Metal Insulator Semiconductor) transistor for charging and discharging the capacitor. A thermal processing at about 800xc2x0 C. (formation of a thermal oxide film) is required to form the capacity insulating film. Technology for forming the capacity insulating film at a reduced temperature by using a highly dielectric material such as a tantalum oxide film (a lower-temperature process) is under study, but has not reached a practical level. On the other hand, in the logic LSI requiring a high-speed operation, reduction in the gate length of the MIS transistor is an essential requirement. Therefore, a lower-temperature process is required in order to suppress impurity diffusion and thus the short-channel effect. In order to integrate the DRAM and the logic LSI on the same chip, the process must be conducted successively while recognizing the difference in need for the lower-temperature process between the DRAM and the logic LSI.
In this case, in the DRAM having a trench-type memory cell structure, i.e., a structure in which the cell plate electrode and the capacity insulating film of the capacitor are disposed in a trench, the capacitor can be formed before formation of the MIS transistor. Accordingly, even if the respective MIS transistors of the DRAM and the logic LSI are formed in a common process after formation of the capacitor, problems resulting from the difference in need for a reduced process temperature between the DRAM and the logic LSI can be easily avoided. Thus, the trench-type memory cell structure is said to be suitable for the e-DRAM. However, the step for forming the capacitor is complicated, and also reduction in the memory cell size is significantly restricted. Therefore, a stacked memory cell structure employed in many DRAMs, i.e., a structure in which the capacitor is provided above the MIS transistor, has been regarded as appropriate.
In the stacked memory cell structure, the following process has been proposed and practiced in order to avoid the problems due to the thermal processing: first, an MIS transistor of the DRAM memory section and a capacitor provided thereon with an interlayer insulating film therebetween are formed. In this step, a gate electrode and an LDD (Lightly Doped Drain) region of the MIS transistor of the logic section are formed, but high-concentration source/drain regions are not formed yet. Thereafter, the interlayer insulating film covering also the logic section is removed, and the source/drain regions of the MIS transistor of the logic section and the like are formed.
FIGS. 9A to 11B are cross-sectional views illustrating an example of a conventional method for manufacturing an e-DRAM semiconductor device using such a process. More specifically, FIGS. 9A to 9C illustrate from the beginning of the manufacturing process of the semiconductor device to the step of forming a storage node electrode in a DRAM memory section. FIGS. 10A and 10B illustrate from the step of forming a capacitor of the DRAM memory section to the step of removing a first interlayer insulating film and forming a sidewall. FIGS. 11A and 11B illustrate from the step of forming a second interlayer insulating film to the step of forming a wiring layer.
First, in the step of FIG. 9A, an element-isolation insulating film 501 surrounding active regions of a DRAM memory section and a logic section is formed at a silicon substrate 500. Then, a silicon oxide film and a polysilicon film are sequentially deposited on the substrate. Thereafter, these films are patterned to form a gate insulating film 502 and a gate electrode 503 of each MIS transistor of the DRAM memory section and the logic section. At this time, a gate line 504 connected to the gate electrode 503 of the logic section and a gate line 505 connected to the gate electrode 503 of the DRAM memory section are formed on the element-isolation insulating film 501. Then, impurities are introduced into the active regions of the logic section and the DRAM memory section by ion implantation or the like, thereby forming LDD regions 507 of the MIS transistor of the logic section as well as source/drain regions 508 of the MIS transistor (memory cell transistor) of the DRAM memory section.
In the step of FIG. 9B, a thin silicon nitride film 509 is deposited on the substrate so as to cover the gate electrodes 503 and the gate lines 504, 505. Then, a first interlayer insulating film 510 of a silicon oxide film is deposited on the substrate. After planarizing the first interlayer insulating film 510, contact holes are formed in the DRAM memory section so as to extend through the first interlayer insulating film 510 and the silicon nitride film 509 to the source/drain regions 508 and the gate line 505, respectively. At this time, no contact hole is formed in the logic section. Then, each contact hole is filled with a conductor film (e.g., a polysilicon film or a tungsten film), thereby forming a conductor plug 511a (part of a storage node) connected to the source of the source/drain regions 508 of the MIS transistor of the DRAM memory section, a conductor plug 511b (bit-line contact) connected to the drain of the source/drain regions 508, and a conductor plug 511c (word-line contact) connected to the gate line 505. Note that the conductor plugs 511b, 511c are not necessarily formed in the cross section of FIG. 9B and FIGS. 9C to 11B described below, but are shown as being present in this cross section for better understanding.
Then, in the step of FIG. 9C, a thin silicon nitride film 512 is formed on the substrate so as to cover the first interlayer insulating film 510 and the conductor plugs 511a to 511c. Thereafter, a silicon oxide film 513 is deposited on the substrate. The silicon oxide film 513 and the silicon nitride film 512 are selectively removed to form an opening such that the conductor plug 511a on the source of the source/drain regions 508 of the DRAM memory section is exposed at the bottom of the opening. Then, a polysilicon film and a photoresist film are formed on the substrate, and the top surface of the substrate is planarized by using an etch-back method. Thus, a bottomed cylindrical storage node electrode 514 of the polysilicon film as well as a photoresist portion 550 that fills a recess formed by the storage node electrode 514 are formed in the opening.
In the step of FIG. 10A, the photoresist portion 550 is removed by ashing or the like, and then the silicon oxide film 513 is selectively removed using hydrofluoric acid or the like. Then, a very thin silicon nitride film is deposited on the substrate, and the surface of the silicon nitride film thus deposited is oxidized to form a capacity insulating film 515 on the storage node electrode 514. Note that, although not shown in FIG. 10A, a stacked layer of the silicon nitride film and the silicon oxide film is formed also on the silicon nitride film 512. Then, a polysilicon film is deposited on the substrate, and a photoresist film 551 is formed so as to cover the DRAM memory section as well as expose the logic section. The polysilicon film and the silicon nitride film 512 are removed in the logic section by anisotropic dry etching using the photoresist film 551 as a mask, thereby forming a cell plate electrode 516 on the silicon nitride film 512.
In the step of FIG. 10B, the photoresist film 551 is removed. Then, by using the cell plate electrode 516 as a mask, the first interlayer insulating film 510 is selectively removed by wet etching with hydrofluoric acid. Thereafter, the exposed portion of the silicon nitride film 509 on the substrate is anisotropically etched (dry etched) to form sidewalls on the respective side surfaces of the gate electrode 503 and the gate line 504 of the logic section. Impurities are then introduced into the active regions of the logic section by ion implantation or the like, thereby forming high-concentration source/drain regions 517 outside the LDD regions 507.
In the step of FIG. 11A, a second interlayer insulating film 518 of a silicon oxide film is deposited on the substrate. Then, contact holes 519 are formed in the DRAM memory section so as to extend through the second interlayer insulating film 518, the cell plate electrode 516 and the silicon nitride film 512 to the conductor plug 511b (bit-line contact) on the drain of the source/drain regions 508 and the conductor plug 511c (word-line contact) on the gate line 505, respectively. A silicon oxide film is then deposited on the substrate and anisotropically etched to form an oxide-film sidewall 520 on the side surface of each contact hole 519.
In the step of FIG. 11B, contact holes are formed in the logic section so as to extend through the second interlayer insulating film 518 to the high-concentration source/drain regions 517 and the gate line 504, respectively. Then, a conductor plug 521 filling each contact hole 519 of the DRAM memory section as well as a conductor plug 522 filling each contact hole of the logic section are simultaneously formed. A wiring 523 of an aluminum alloy film or the like is formed on the second interlayer insulating film 518 so as to be connected to each conductor plug 521, 522.
In this manufacturing method, a capacitor of the DRAM memory section can be formed before formation of the high-concentration source/drain regions 517 of the MIS transistor of the logic section. Therefore, diffusion of the impurities in the high-concentration source/drain regions 517 of the MIS transistor of the logic section can be suppressed. As a result, reduction in a threshold voltage due to the short-channel effect of the MIS transistor of the logic section is suppressed, whereby high-speed operation can be retained with sufficient voltage application to the gate electrode.
It is an object of the invention to provide a semiconductor device that has a reduced area of a DRAM memory section by preventing a void region Rvo from being produced in the DRAM memory section, and thus includes a DRAM integrating memory cells at a higher density, and a manufacturing method of the same.
A semiconductor device of the present invention includes: a semiconductor substrate having an active region; an element-isolation insulating film provided on the semiconductor substrate so as to surround the active region; a gate insulating film and a gate electrode which are provided on the active region of the semiconductor substrate; source/drain regions respectively provided in regions located on both sides of the gate electrode within the semiconductor substrate; an interlayer insulating film provided on the semiconductor substrate; a storage node having an electrode portion extending on the interlayer insulating film and a plug portion extending through the interlayer insulating film so as to be connected to the source/drain region; a capacity insulating film provided on the electrode portion of the storage node; a cell plate electrode facing the electrode portion of the storage node with the capacity insulating film interposed therebetween; and an annular etch stopper member formed from a material resistant to an etchant of the interlayer insulating film, and provided under the cell plate electrode so as to surround the active region along a periphery of the cell plate electrode, wherein the semiconductor device functions as a DRAM (Dynamic Random Access Memory) memory cell.
Since the etch stopper member having a high etching selection ratio to the interlayer insulating film is provided under the cell plate electrode. Therefore, the interlayer insulating film located under the cell plate electrode will not be etched in the manufacturing process. Accordingly, a dimensional margin in preparation for partial removal of the interlayer insulating film under the cell plate electrode need not be provided for the cell plate electrode, allowing for reduction in the area of the DRAM memory section.
The etch stopper member may include a dummy gate line provided on the element-isolation insulating film and formed from the same material as that of the gate electrode. This enables the etch stopper member to be provided without increasing the number of steps, thereby preventing increase in manufacturing costs.
The etch stopper member may be a cylindrical wall extending through the interlayer insulating film so as to be in contact with the element-isolation insulating film, and formed from the same material as that of the plug portion of the storage node. This also enables the etch stopper member to be provided without increasing the number of steps, thereby preventing increase in manufacturing costs.
The etch stopper member may be formed from a dummy gate line and a cylindrical wall, the dummy gate line being provided on the element-isolation insulating film and formed from the same material as that of the gate electrode, and the cylindrical wall extending through the interlayer insulating film so as to be in contact with the dummy gate line, and formed from the same material as that of the plug portion of the storage node. Thus, the aforementioned effects can be more effectively obtained.
A logic transistor including a gate insulating film, a gate electrode and source/drain regions may be provided on the semiconductor substrate. This enables reduction in the area of the DRAM memory section in a semiconductor device incorporating a DRAM and logic.
A method for manufacturing a semiconductor device according to the invention includes the steps of: (a) forming an element-isolation insulating film surrounding first and second active regions of a semiconductor substrate; (b) depositing a gate insulating film and a polysilicon film on the substrate, and then patterning the polysilicon film so as to form first and second gate electrodes on the first and second active regions, respectively; (c) introducing impurities into regions located on both sides of each of the first and second electrodes in the first and second active regions within the semiconductor substrate so as to form first and second source/drain regions, respectively; (d) forming an interlayer insulating film on the substrate; (e) forming in the first interlayer insulating film a first contact hole extending to each of the first source/drain regions; (f) forming a storage node from both a plug portion filling the first contact hole and an electrode portion extending on the interlayer insulating film; (g) forming a capacity insulating film on the electrode portion of the storage node; (h) forming a cell plate electrode facing the electrode portion of the storage node with the capacity insulating film interposed therebetween; (i) etching the interlayer insulating film using the cell plate electrode as a mask, thereby exposing the second gate electrode; and (j) forming, prior to the step (g), an etch stopper member under the cell plate electrode so as to surround the first active region along a periphery of the cell plate electrode, the etch stopper member being formed from a material that is resistant to an etchant of the interlayer insulating film.
According to this method, the etch stopper member having a high etching selection ratio to the interlayer insulating film is formed under the cell plate electrode in the step (j). Therefore, the first interlayer insulating film located under the cell plate electrode will not be etched in the step (i). Accordingly, a dimensional margin in preparation for partial removal of the interlayer insulating film under the cell plate electrode need not be provided for the cell plate electrode, allowing for reduction in the area of the DRAM memory section.
The step (j) may be conducted by patterning the polysilicon film in the step (b) so as to form on the element-isolation insulating film a dummy gate line extending along a periphery of a region where the cell plate electrode is to be formed. Alternatively, the step (j) may be conducted by: forming on the element-isolation insulating film a cylindrical groove extending through the first interlayer insulating film in the step (e); and filling the cylindrical groove with the same material as that of the plug portion of the storage node in the step (f). Alternatively, the step (j) may be conducted by: patterning the polysilicon film in the step (b) so as to form on the element-isolation insulating film a dummy gate line extending along a periphery of a region where the cell plate electrode is to be formed; forming on the element-isolation insulating film a cylindrical groove extending through the first interlayer insulating film to the dummy gate line in the step (e); and filling the cylindrical groove with the same material as that of the plug portion of the storage node in the step (f). This enables reduction in the area of the DRAM memory section without increasing the number of steps.